01 Problem
Make dismissing the alarm an active task.
The goal was to build an alarm that would not stop from a simple button press. Instead, the user had to solve a basic arithmetic question, turning alarm dismissal into a small interaction that required attention.
02 Architecture
Two FPGA boards, one completion signal.
The system split responsibility across two FPGA boards connected through physical I/O pins. One board handled the arithmetic question, showed it across multiple seven-segment displays, and checked the submitted answer. When the answer was correct, it sent a signal to the second board, which controlled and stopped the buzzer alarm.
03 Implementation
Designed directly from logic gates.
Using Xilinx design software, I constructed and programmed the behavior manually from logic gates rather than writing Verilog or VHDL. The design combined arithmetic generation, seven-segment display control, answer checking, and the state needed to keep the alarm active until the correct result was received.
The second board drove a buzzer through a resistor-limited circuit. The exact FPGA board models and Xilinx application are no longer recorded.
04 Engineering challenge
Coordinate behavior across hardware boundaries.
The important systems problem was not only evaluating the answer, but making two independently programmed FPGA boards behave as one reliable device. The alarm board had to remain active until it received the expected signal from the question board.
05 What I learned
Complex behavior begins with simple logic.
This project gave me hands-on experience translating desired system behavior into gates and signals. It also introduced an idea that still matters in software systems: define clear component responsibilities and a precise interface between them.